* SRDT test $Id$
sysclear
archmode esame
r 1a0=00000001800000000000000000000200 # z/Arch restart PSW
r 1d0=0002000180000000000000000000DEAD # z/Arch pgm new PSW
r 200=B7000320     # LCTL R0,R0,CTLR0  Set CR0 bit 45
r 204=41000006     # LA R0,6           R0=Number of test data
r 208=41100380     # LA R1,TEST1       R1=>Test data table
r 20C=41F00400     # LA R15,RES1       R15=>Result table
r 210=68601000     #A LD F6,0(,R1)     Load FPR6=TESTn
r 214=41200004     # LA R2,4           R2=Number of shift tests
r 218=41300340     # LA R3,N1          R3=>Shift count table
r 21C=58403000     #B L R4,0(,R3)      Load R4=Nn
r 220=ED6040008040 # SLDT F8,F6,0      Shift FPR6 left Nn digits
r 226=6080F000     # STD F8,0(,R15)    Store F8 in result table
r 22A=41F0F008     # LA R15,8(,R15)    R15=>next result table
r 22E=B3E200E8     # CUDTR R14,F8      Convert to BCD R14 from FPR8
r 232=E3E0F0000024 # STG R14,0(,R15)   Store R14 in result table
r 238=41F0F008     # LA R15,8(,R15)    R15=>next result table
r 23C=ED6040008041 # SRDT F8,F6,0      Shift FPR6 right Nn digits
r 242=6080F000     # STD F8,0(,R15)    Store F8 in result table
r 246=41F0F008     # LA R15,8(,R15)    R15=>next result table
r 24A=B3E200E8     # CUDTR R14,F8      Convert to BCD R14 from FPR8
r 24E=E3E0F0000024 # STG R14,0(,R15)   Store R14 in result table
r 254=41F0F008     # LA R15,8(,R15)    R15=>next result table
r 258=41303004     # LA R3,4(,R3)      R3=>Next Nn
r 25C=4620021C     # BCT R2,B          Loop to end of Nn table
r 260=41101008     # LA R1,8(,R1)      R1=>Next TESTn
r 264=46000210     # BCT R0,A          Loop to end of TESTn table
r 268=41000400     # LA R0,RES1        R0->Actual results
r 26C=41100300     # LA R1,6*4*32      R1=Length of results table
r 270=EC20100000DA # ALHSIK R2,R0,4096 R2->Expected results (R2=R0+X'1000')
r 276=1831         # LR R3,R1          R3=Length of results table
r 278=0F02         # CLCL R0,R2        Compare with expected results
r 27A=A7740004     # JNE *+8           Error if not equal
r 27E=B2B20300     # LPSWE WAITPSW     Load enabled wait PSW
r 282=B2B20310     # LPSWE DISWAIT     Load disabled wait PSW
r 300=07020001800000000000000000AAAAAA # WAITPSW Enabled wait state PSW
r 310=00020001800000000000000000BADBAD # DISWAIT Disabled wait state PSW
r 320=00040000     # CTLR0             Control register 0 (bit45 AFP control)
r 340=00000000     # N1 DC F'0'    Shift count 0
r 344=FFFFFFC1     # N2 DC F'1'    Shift count 1 in low-order 6 bits
r 348=000002C4     # N3 DC F'708'  Shift count 4 in low-order 6 bits
r 34C=0000003F     # N4 DC F'63'   Shift count 63
r 380=2238000000000000 # TEST1 DC DD'0' Zero positive
r 388=2238000012045078 # TEST2 DC DD'220214078' Normal positive 
r 390=ABCDEF0123456789 # TEST3 DC DD'-2.989004434259709E116' Large negative
r 398=7CABCDEF01234567 # TEST4 DC DD'QNAN' QNaN positive 
r 3A0=FE0000000000ABCD # TEST5 DC DD'-SNAN' SNaN negative
r 3A8=78123456789ABCDE # TEST6 DC DD'INF' Infinity positive
* Expected results
r 1400=22380000 00000000 00000000 00000000 # 0 << 0
r 1410=22380000 00000000 00000000 00000000 # 0 >> 0
r 1420=22380000 00000000 00000000 00000000 # 0 << 1
r 1430=22380000 00000000 00000000 00000000 # 0 >> 1
r 1440=22380000 00000000 00000000 00000000 # 0 << 4
r 1450=22380000 00000000 00000000 00000000 # 0 >> 4
r 1460=22380000 00000000 00000000 00000000 # 0 << 63
r 1470=22380000 00000000 00000000 00000000 # 0 >> 63
r 1480=22380000 12045078 00000002 20214078 # 220214078 << 0
r 1490=22380000 12045078 00000002 20214078 # 220214078 >> 0
r 14A0=22380000 9023038A 00000022 02140780 # 220214078 << 1
r 14B0=22380000 02208607 00000000 22021407 # 220214078 >> 1
r 14C0=22380240 8C0E2800 00022021 40780000 # 220214078 << 4
r 14D0=22380000 00008821 00000000 00022021 # 220214078 >> 4
r 14E0=22380000 00000000 00000000 00000000 # 220214078 << 63
r 14F0=22380000 00000000 00000000 00000000 # 220214078 >> 63
r 1500=ABCCEF01 23456789 29890044 34259709 # -2989004434259709 << 0
r 1510=ABCCEF01 23456789 29890044 34259709 # -2989004434259709 >> 0
r 1520=EFCC1E11 1C2BEC1A 98900443 42597090 # -2989004434259709 << 1
r 1530=A3CD5E23 243894FC 02989004 43425970 # -2989004434259709 >> 1
r 1540=A3CC4470 AFB06800 00443425 97090000 # -2989004434259709 << 4
r 1550=A3CC0057 88C90E25 00002989 00443425 # -2989004434259709 >> 4
r 1560=A3CC0000 00000000 00000000 00000000 # -2989004434259709 << 63
r 1570=A3CC0000 00000000 00000000 00000000 # -2989004434259709 >> 63
r 1580=7C03CDEF 01234567 09479360 12151267 # QNaN << 0
r 1590=7C03CDEF 01234567 09479360 12151267 # QNaN >> 0
r 15A0=7C027978 0A1A4B70 04793601 21512670 # QNaN << 1
r 15B0=7C005AEE F01454A6 00947936 01215126 # QNaN >> 1
r 15C0=7C01E028 692DC000 03601215 12670000 # QNaN << 4
r 15D0=7C000016 BBBC0515 00000947 93601215 # QNaN >> 4
r 15E0=7C000000 00000000 00000000 00000000 # QNaN << 63
r 15F0=7C000000 00000000 00000000 00000000 # QNaN >> 63
r 1600=FE000000 0000ABCD 00000000 00082947 # -SNaN << 0
r 1610=FE000000 0000ABCD 00000000 00082947 # -SNaN >> 0
r 1620=FE000000 0004BE70 00000000 00829470 # -SNaN << 1
r 1630=FE000000 0000215A 00000000 00008294 # -SNaN >> 1
r 1640=FE000000 12F9C000 00000008 29470000 # -SNaN << 4
r 1650=FE000000 00000008 00000000 00000008 # -SNaN >> 4
r 1660=FE000000 00000000 00000000 00000000 # -SNaN << 63
r 1670=FE000000 00000000 00000000 00000000 # -SNaN >> 63
r 1680=78023456 789ABCDE 04342597 09949198 # Inf << 0
r 1690=78023456 789ABCDE 04342597 09949198 # Inf >> 0
r 16A0=7801C2BE C5F86C8E 03425970 99491980 # Inf << 1
r 16B0=78004389 4FCA78BF 00434259 70994919 # Inf >> 1
r 16C0=7802FB17 E1B23800 05970994 91980000 # Inf << 4
r 16D0=78000010 E253F29E 00000434 25970994 # Inf >> 4
r 16E0=78000000 00000000 00000000 00000000 # Inf << 63
r 16F0=78000000 00000000 00000000 00000000 # Inf >> 63
ostailor null
restart
pause 1
* Display test data
r 340.10 
r 380.30 
* Display actual results
r 400.300
