* CZXT,CZDT test $Id$
sysclear
archmode esame
r 1a0=00000001800000000000000000000200 # z/Arch restart PSW
r 1d0=0002000180000000000000000000DEAD # z/Arch pgm new PSW
r 200=B7000310     # LCTL R0,R0,CTLR0  Set CR0 bit 45
r 204=B2BD0314     # LFAS FPCREG       Load value into FPC register
r 208=68300340     # LD F3,TEST1       Load 123
r 20C=ED03040030A8 # CZDT F3,STR1(4),0  Convert to unsigned zoned
r 212=ED03040438A8 # CZDT F3,STR2(4),8  Convert to signed zoned
r 218=ED03040834A8 # CZDT F3,STR3(4),4  Convert to ASCII zoned
r 21E=ED03040C3AA8 # CZDT F3,STR4(4),10 Convert to signed with F zone
r 224=68300348     # LD F3,TEST2       Load 1234567898765432
r 228=ED0F041038A8 # CZDT F3,STR5(16),8 Convert to signed zoned
r 22E=ED07042038A8 # CZDT F3,STR6(8),8  Convert to zoned with overflow
r 234=68300350     # LD F3,TEST3       Load -12345678
r 238=ED07042832A8 # CZDT F3,STR7(8),2  Convert to unsigned zoned
r 23E=ED0704303AA8 # CZDT F3,STR8(8),10 Convert to signed zoned
r 244=68300358     # LD F3,TEST4       Load -0
r 248=ED03043838A8 # CZDT F3,STR9(4),8  Convert to signed zoned with D zone
r 24E=ED01043C39A8 # CZDT F3,STR10(2),9 Convert to signed zoned with C zone
r 254=ED01043E3BA8 # CZDT F3,STR11(2),11 Convert to signed zoned with F zone
r 25A=68500360     # LD F5,TEST5       Load extended...
r 25E=68700368     # LD F7,TEST5+8     ...123
r 262=ED07044050A9 # CZXT F5,STR12(8),0 Convert to unsigned zoned
r 268=68400370     # LD F4,TEST6       Load extended...
r 26C=68600378     # LD F6,TEST6+8     ...-12345678
r 270=ED07044848A9 # CZXT F4,STR13(8),8 Convert to signed zoned
r 276=68900380     # LD F9,TEST7       Load extended...
r 27A=68B00388     # LD F11,TEST7+8     ...+123...892
r 27E=ED2104509CA9 # CZXT F9,STR14(34),12 Convert to signed ASCII zoned
r 284=D56F04000500 # CLC STR1(96),VER1 Compare with expected result
r 28A=477002FC     # BNE ERROR         Error if not equal
r 28E=B2B20300     # LPSWE WAITPSW     Load enabled wait PSW
r 2FC=B2B201D0     # LPSWE PGMNEW      Load disabled wait PSW
r 300=07020001800000000000000000FED0D0 # WAITPSW Enabled wait state PSW
r 310=00040000     # CTLR0             Control register 0 (bit45 AFP control)
r 314=00000000     # FPCREG            Floating point control register
r 340=22380000000000A3 # TEST1 DC DD'123'
r 348=263934B9C7EF9632 # TEST2 DC DD'1234567898765432'
r 350=A238000001271778 # TEST3 DC DD'-12345678'
r 358=A238000000000000 # TEST4 DC DD'-0'
r 360=220800000000000000000000000000A3 # TEST5 DC DX'123'
r 370=A2080000000000000000000001271778 # TEST6 DC DX'-12345678'
r 380=2608134B9C7EF963228E56E2D34B9D1E # TEST7 DC DX'123...892'
r 400=00000000000000000000000000000000 # STR1 DC 16X'00'
r 410=00000000000000000000000000000000 # STR5 DC 16X'00'
r 420=00000000000000000000000000000000 # STR6 DC 16X'00'
r 430=00000000000000000000000000000000 # STR8 DC 16X'00'
r 440=00000000000000000000000000000000 # STR12 DC 16X'00'
r 450=00000000000000000000000000000000 # STR14 DC 16X'00'
r 460=00000000000000000000000000000000 #  DC 16X'00'
r 500=F0F1F2F3     # VER1 DC C'0123'
r 504=F0F1F2C3     # VER2 DC Z'+0123'
r 508=30313233     # VER3 DC CA'0123'
r 50C=F0F1F2F3     # VER4 DC C'0123'
r 510=F1F2F3F4F5F6F7F8F9F8F7F6F5F4F3C2 # VER5 DC Z'+1234567898765432'
r 520=F9F8F7F6F5F4F3C2 # VER6 DC Z'+98765432'
r 528=F1F2F3F4F5F6F7F8 # VER7 DC C'12345678'
r 530=F1F2F3F4F5F6F7D8 # VER8 DC Z'-12345678'
r 538=F0F0F0D0     # VER9 DC ZL4'-0'
r 53C=F0C0         # VER10 DC ZL2'+0'
r 53E=F0F0         # VER11 DC CL2'00'
r 540=F0F0F0F0F0F1F2F3 # VER12 DC C'00000123'
r 548=F1F2F3F4F5F6F7D8 # VER13 DC Z'-12345678'
r 550=31323334353637383938373635343332 # VER14 DC CA'1234567898765432'
r 560=31323334353637383132333435363738 #  DC CA'1234567812345678'
r 570=39C20000000000000000000000000000 #  DC CA'9',Z'+2',14X'00'
s+
restart
