%FILENAME%
vtr-9.0.0-1.0-pentium4.pkg.tar.zst

%NAME%
vtr

%BASE%
vtr

%VERSION%
9.0.0-1.0

%DESC%
Verilog to Routing -- Open Source CAD Flow for FPGA Research

%CSIZE%
7119522

%ISIZE%
25723936

%SHA256SUM%
6f729cb3cbdf2542cda9f1b027d2192dd60b336f839cb4c7f6613e6764b6ba19

%URL%
https://verilogtorouting.org

%LICENSE%
MIT

%ARCH%
pentium4

%BUILDDATE%
1755381258

%PACKAGER%
Andreas Baumann <mail@andreasbaumann.cc>

%DEPENDS%
ctags
tbb

%MAKEDEPENDS%
cmake
wget

